Senior Verification Engineer

2 Days Old

Job Description

Job Description
Requirements
  • 6+ years of experience a must
  • Performed at last 2 or more full block/system verification cycles.
  • In depth knowledge in VLSI verification flow, languages and concepts.
  • Experience in data path or data protocols, specifically Ethernet - preferred
  • Verification using one of the known methodologies (eRM, UVM, OVM).

Responsibilities

  • Plan and perform the verification of digital design blocks according to the design specification and interacting with design engineers.
  • Build verification environments using SystemVerilog and UVM.
  • Identify and write all types of coverage measures for corner-cases.
  • Debug the functionality with design engineers.
  • Perform coverage collection and follow the metrices to close the full functionality.

Required Citizenship / Work Permit / Visa Status
Will sponsor H1-B

Must-Haves
-On-site in Austin, TX, five days a week.
-Performed at least 2 or more full block/system verification cycles.
-In depth knowledge in VLSI verification flow, languages and concepts.

Apply
Location:
Austin
Category:
Technology

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